Welcome to IEEE TCCA Email-Monthly, Sept. 2003: 1. PACT'03 The Twelfth International Conference on Parallel Architectures and Compilation Techniques *September 27 - October 1, 2003 Chateau Sonesta Hotel, New Orleans, Louisiana, USA *EARLY REGISTRATION ENDS on 12 Sep midnight PDT -Submitted by: Dieter Kranzlmueller -CALL FOR PARTICIPATION: http://www.pactconf.org 2. NP3 - 2004 Workshop on Network Processors & Applications *February 14-15, 2004, Madrid, Spain. *Workshop URL : http://www.cse.wustl.edu/NP3 -submitted by: Haldun Hadimioglu 3. RAW 2004 The 11th Reconfigurable Architectures Workshop *April 26-27, 2004, Santa Fe, New Mexico *Submission Deadline: October 3, 2003 -Submitted by: R. Vaidyanathan -CALL FOR PAPERS: http://www.ece.lsu.edu/vaidy/raw04/ 4. Boundaryless Information Flow & Enterprise Architecture *October 20-21, 2003, Washington DC *Submission Deadline: Sept. 19, 2003 -Submitted by: Maryann Karinch The Open Group -CALL FOR PAPERS: http://www.opengroup.org/cio/CallForPapers.htm 5. ISCA-2004 International Symposium on Computer Architecture *June 19-23, 2004, Munich, Germany, *Abstract submission deadline: Oct 31, 2003 -CALL FOR PAPERS: http://isca.in.tum.de/ ------- ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --- CALL FOR PARTICIPATION -- PACT 2003 -- http://www.pactconf.org --- The Twelfth International Conference on Parallel Architectures and Compilation Techniques September 27 - October 1, 2003 Chateau Sonesta Hotel, New Orleans, Louisiana, USA EARLY REGISTRATION ENDS on 12 Sep midnight PDT (13 Sep 07:00 UTC) NEW!!NEW!!NEW!! Conference room rate guaranteed until September 12. NEW!!NEW!!NEW!! PACT is a multi-disciplinary conference on hardware and software approaches to parallelism ranging across instruction-level parallelism, thread-level parallelism, multiprocessor parallelism and distributed systems. There are 24 papers in the main program, selected from 144, and keynotes by: - Monica Lam, Stanford University "Challenges and New Approaches to Program Analysis" - Guri Sohi, University of Wisconsin, Madison "Single-Chip Multiprocessors: The Rebirth of Parallel Computing" - Chris Johnson, University of Utah "Biomedical Computing and Visualization" For the complete program visit http://www.ccs.neu.edu/pact03/program.html There will be a Work in Progress session and: Workshops * Adaptive Grid Middleware * MEmory performance: DEaling with Applications, systems and architectures * Compilers and Operating Systems for Low Power * Storage Network Architecture and Parallel I/Os * Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing Tutorials * Architectures, Languages, and Compilers for the Streaming Domain Saman Amarasinghe (MIT), Bill Thies (MIT) * UPC: Unified Parallel C T. El-Ghazawi (George Washington Univ.), W. Carlson (IDA Ctr for CS) * Architecture and Compiler Support for Speculative Precomputation Donald Yeung (UMCP), Dean Tullsen (UCSD), and Steve Shih-wei Liao (Intel) * OpenMP Implementation and Performance Issues Mats Brorsson, and Sven Karlsson, (KTH Sweden) * Understanding Your Results: Statistical Tools for Computer Performance Measurement and Simulation David J. Lilja (University of Minnesota) PACT 2003 is being held in New Orleans, LA, a vibrant city rich in culture and tradition. The conference banquet will be held at the Cabildo Museum, site of the signing of the Louisiana Purchase in 1803. PACT 2003 is sponsored by IFIP WG 10.3, IEEE TCCA, IEEE TCPP, and ACM SIGARCH. Student travel grants are available. For more information and online registration, visit http://www.pactconf.org. -------------------------------------------------------------------------- ______________________________________________________________________________ ********************************************************* * * * 1st CALL FOR PAPERS * * * * * * The 11th Reconfigurable Architectures Workshop * * * * RAW 2004 * * * * April 26 - 27, 2004, Santa Fe, New Mexico * * * * * * Submission Deadline: October 3, 2003 * * * * http://www.ece.lsu.edu/vaidy/raw04/ * * * ********************************************************* The 11th Reconfigurable Architectures Workshop (RAW 2004) will be held at the Eldorado Hotel Santa Fe, New Mexico on Monday, April 26, and Tuesday April 27 2004. RAW 2004 is associated with the 18th Annual International Parallel and Distributed Processing Symposium (IPDPS 2004) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing. RAW 2004 is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing. The main focus of the workshop is on Run-Time & Dynamic Reconfiguration: Architectures, Algorithms, Technologies Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse-grain FPFAs) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2004 aims to provide a forum for creative and productive interaction between all these disciplines. Topics of Interest: Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications). The topics of interest include, but are not limited to: Models & Architectures * Theoretical Models (R-Mesh, etc.) * RTR Models and Systems * RTR Hardware Architectures * Optical Interconnect Models * Simulation and Prototyping * Bounds and Complexity Issues Algorithms & Applications * Algorithmic Techniques * Mapping Parallel Algorithms * Distributed Systems & Networks * Fault Tolerance Issues * Wireless and Mobile Systems * Automotive Applications, etc. Technologies & Tools * Configurable Systems-on-Chip * Energy Efficiency Issues * Devices and Circuits * Reconfiguration Techniques * High Level Design Methods * System support Submission Guidelines: Authors should submit by email an electronic version of their work by October 3, 2003 to Serge Vernalde, IMEC, Belgium (vernalde@imec.be) AND register their paper through our web-interface at http://www.ece.lsu.edu/vaidy/raw04/ All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript (not to exceed 8 pages of single spaced text, including figures and tables) or, in special cases, may be a summary of relevant work. Submissions should be in pdf-format (preferred), or alternatively in Postscript (level 2) format. Authors should make sure that the submission can be viewed using ghostscript and will print on standard letter size paper (8.5" x 11"). The IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press as a CD-ROM disk. Important Dates: Manuscript due: October 3, 2003 Notification of acceptance/rejection: November, 2003 Final version due: January, 2004 Organization: Program Chair: Serge Vernalde, IMEC, Belgium (vernalde@imec.be) Workshop Chair: Juergen Becker, Universitat Karlsruhe (TH), Germany (becker@itiv.uni-karlsruhe.de) Steering Chair: Viktor K. Prasanna, University of Southern California, USA (prasanna@ganges.usc.edu) Publicity Chair (USA): Ramachandran Vaidyanathan, Louisiana State University, USA (vaidy@ece.lsu.edu) Publicity Chair (Europe, Asia): Reiner Hartenstein, Kaiserslautern University of Technology, Germany (reiner@hartenstein.de) Program Committee: Jeffrey Arnold, Adaptive Silicon, Inc., USA Juergen Becker, Universitat Karlsruhe (TH), Germany Neil Bergmann, University of Queensland, Australia Christophe Bobda, Universitat Erlangen-Nurnberg, Germany Don Bouldin, University of Tennessee, USA Gordon Brebner, University of Edinburgh, UK Klaus Buchenrieder, Infineon Technologies, Germany Thomas Buchner, IBM, Germany Oliver Diessel, University of New South Wales, Australia Carl Ebeling, University of Washington, USA Hossam ElGindy, University of New South Wales, Australia Manfred Glesner, Darmstadt University of Technology, Germany Steve Guccione, Quicksilver Technology, USA Herbert Gruenbacher, Vienna University of Technology, Austria Wolfram Hardt, Technische Universitat Chemnitz, Germany Reiner Hartenstein, University of Kaiserslautern, Germany Ulrich Heinkel, Lucent Technologies, Germany Mark Jones, Virginia Tech, USA Peter Jung, Gerhard Mercator University, Duisburg, Germany Mohammed A. S. Khalid, Cadence Design Systems, USA Hyoung-Joong Kim, Kangwon National University, Korea Fabrice Kordon, Université Pierre & Marie Curie, Paris, France Rainer Kress, Infineon Technologies, Germany Markus Kuehl, Forschungszentrum Informatik (FZI), Karlsruhe, Germany Rudy Lauwereins, IMEC, Leuven, Belgium Philip Leong, Chinese University of Hong Kong, China Marnane Liam, University College, Ireland Rong Lin, State University of New York, Geneseo, USA Wayne Luk, Imperial College, UK Juergen Luka, DaimlerChrysler AG, Germany Patrick Lysaght, Xilinx, USA Malgorzata Marek-Sadowska, University of California, Santa Barbara, USA John McHenry, National Security Agency, USA Alessandro Mei, University Rome "La Sapienza", Italy Martin Middendorf, Katholische Universität Eichstätt, Germany George Milne, University of Western Australia, Australia Toshiaki Miyazaki, NTT Network Innovation Labs., Japan Amar Mukherjee, University of Central Florida, USA Dietmar Meuller, Technische Universitat Chemnitz, Germany Koji Nakano, Hiroshima University, Japan Marco Platzner, Swiss Federal Institute of Technology (ETH) Zuerich, Bernard Pottier, Université de Bretagne Occidentale, France Ranjani Parthasarathi, School of Computer Science and Engineering, Michel Renovell, LIRMM, France Franz Rammig, Universitat Paderborn, Germany Peter Roth, IBM, Germany Sakir Sezer, Queen's University, N. Ireland, U.K. John Schewel, Virtual Computer Corp., USA Hartmut Schmeck, Universität Karlsruhe (TH), Germany Gerard Smit, University of Twente, The Netherlands V. Sridhar, Satyam Computer Services Ltd., India Juergen Teich, Friedrich-Alexander-Universitaet Erlangen, Germany Lionel Torres, LIRMM, Montpellier, France Jim Torresen, University of Oslo, Norway Jerry L. Trahan, Louisiana State University, USA Ramachandran Vaidyanathan, Louisiana State University, USA Milan Vasilko, Bournemouth University, UK Stamatis Vassiliadis, Delft University of Technology, The Netherlands Serge Vernalde, IMEC, Belgium Martin Vorbach, PACT Informationstechnologie, Germany K. Waldschmidt, Universitat Frankfurt, Germany Norbert Wehn, University of Kaiserslautern, Germany Peixin Zhong, Lucent Technologies, USA Hans Christoph Zeidler, Universitat der Bundeswehr Hamburg, Germany RAW 2004 11th Reconfigurable Architectures Workshop Monday, 26 April and Tuesday, 27 April, 2004 Eldorado Hotel,Santa Fe, New Mexico, USA http://www.ece.lsu.edu/vaidy/raw04/ 1st Call For Papers Submission Deadline: October 3, 2003 For more information e-mail: info@ipdps.org -------------------------------------------------------------------------- The Open Group's Boundaryless Information FlowTM Reference Architecture Initiative Boundaryless Information Flow & Enterprise Architecture October 20-21 Washington DC Call For Boundaryless Information Flow Architecture Papers The Open Group is soliciting papers and presentations from vendors and other technology providers addressing "Architectures for Boundaryless Information Flow." Papers are to describe architectural approaches addressing one or more of six models of Boundaryless Information Flow, which are described in the paper "Boundaryless Information Flow Reference Architecture: Six Example Boundaryless Business Models." (.doc 549kb) (.pdf 257kb). Preference will be given to papers describing approaches to achieving Boundaryless Information Flow that are based on available technology, or technologies that will be available in the near term. All papers accepted will be published as part of the proceedings of The Open Group's Quarterly Members Conference in Washington, DC, October 20-21, 2003. Authors of selected papers will be given the opportunity to present their papers at the meeting. Some papers may be presented in workshops during the meeting, or in related meetings that take place during the same week. All submitted papers may be used in any medium in whole or in part (published in print or web as submitted, either individually, or in combination with other works), as source material by The Open Group in the creation and/or documentation of "Boundaryless Information Flow Reference Architectures," and by submitting a paper, the submitter agrees to such use without the need for any further permission. To apply for participation please send an email request to boundaryless@opengroup.org indicating: Presenter's name: Company/organization details: Company/organization contacts: Which model or models you will address: The architectural approach, architecture or subsystem architecture you will present: Please note: We are seeking presentations that describe technical architectures and architectural approaches, and that are addressed to a moderately- to highly-technical audience. The presentation should be an architectural presentation on a vendor or technology provider's given product or product-line that specifically addresses one or more of the given environments described in this paper. Product pitches are not acceptable presentations, but vendors and technology providers should feel free to present their products as exemplars of the architectural approach described. The presentation of the paper should be targeted for 20 minutes. Scope The Problem Organizations that choose to move toward the Boundaryless Organization to improve their operational effectiveness are finding Information Technology resistant. The Open Group is seeking to help organizations address that resistance, thereby achieving Boundaryless Information Flow in support of their movement toward the Boundaryless Organization. Boundaryless Information Flow represents the vision that The Open Group is pursuing. This document takes a step toward that pursuit by providing a framework to elicit, evaluate, and position necessary architectural contributions for Boundaryless Information Flow. The Open Group's Boundaryless Information Flow Reference Architecture The Open Group's vision is ?Boundaryless Information Flow achieved through global interoperability in a secure, reliable and timely manner.? Achieving this vision is not an easy task; the road ahead isn?t necessarily clearly marked. To help the membership of The Open Group engage in efforts to achieve this vision, The Open Group is working to create a set of "Boundaryless Information Flow Reference Architectures." This framework of reference architectures will guide the creation of specific architectures, solutions, and systems for use by companies whose key IT objective is the reduction of the friction of internal and/or external boundaries. It will include descriptions of business strategies, scenarios and profiles to help an organization identify the significance of Boundaryless Information Flow architectures to its business strategy and goals. Each of the Reference Architectures will identify specific architectural techniques and patterns, particularly relevant or appl! icable technologies, and, especially, standards and norms that ensure interoperability, portability, and broad utility of solutions to the challenge of boundarylessness. Within the paper called "Boundaryless Information Flow Reference Architecture: Six Example Boundaryless Business Models" (.doc 549kb) (.pdf 257kb) we describe six specific business models of Boundaryless Information Flow. We also describe the types of subsystem architectures (Common System Architectures) that appear to be particularly significant to these scenarios. That is, the identified subsystem architectures seem to be the ones that would differentiate or define the business model, and that would require the greatest attention when creating a solution in the context of the model. Time Line Aug 8 Call for Papers announcement Aug 9-Sep 19 Submissions accepted Sep 20-Oct 5 Paper reviews Oct 6 Presenter selection and notification Oct 20 - 21 Presentations at Washington Conference Submission Reviewer Team All Submissions will be reviewed by a team of reviewers. The team of reviewers will minimally include: * Terence Blevins, VP and CIO of The Open Group * Eliot Solomon, Principal of Eliot M. Solomon Consulting, Inc. Additional review team members may be added as necessary. Submission requirements Papers must address one or more of six models of Boundaryless Information Flow, which are described in the accompanying paper. The approaches presented should be based on available technology, or technologies that will be available in the near term, and should demonstrate how those technologies will relate to future development and evolution of IT architecture. Papers that address more than one of the six models should treat each model addressed as a separate case. Presentations may describe architectures, architectural elements, standards, or architectural methodologies that are specifically applicable to the model being addressed. When the thing being described is dependent on architectures not specific to the model being addressed (for example, when an element is dependent on a larger architectural framework such as OGSA or "web services," or on a subsystem architecture, such as a specific security, directory, or messaging architecture) that dependency and its (positive and negative) consequences should be clearly described. Ideally, accepted papers will: describe an architectural approach; discuss the relation of that approach to larger architectural issues; indicate what other architectural or design elements beside those presented in the paper would be required to achieve a satisfactory solution; and provide examples of products that could be employed in a manner consistent with the presented approach. Attention should be given to issues of interoperability, portability (of the presented approach and of applications that may rely on it), standards, and the available means to demonstrate or assure conformance to standards and best industry practices. Papers that are less comprehensive that address only current technology, or that are theoretical in nature will be considered for inclusion in the published proceedings of the conference. Papers targeted to specific aspects of Boundaryless Information Flow but not addressing any of the six models may be accepted for use in workshops. Descriptions of specific technologies, especially standards, will similarly be considered for presentation in workshops or technology forums at the Members' Meeting. All submitted papers may be used in any medium in whole or in part (published in print or web as submitted, either individually, or in combination with other works), as source material by The Open Group in the creation and/or documentation of "Boundaryless Information Flow Reference Architectures," and by submitting a paper, the submitter agrees to such use without the need for any further permission. -------------------------------------------------------------------------- --------------------------------------------------------------------- ISCA-2004 Call for Papers The 31st Annual International Symposium on Computer Architecture Munich, Germany, June 19-23, 2004 http://isca.in.tum.de/ --------------------------------------------------------------------- Papers are solicited for the 31st Annual International Symposium on Computer Architecture. Papers are being sought on all aspects of computer architecture, including (but not limited to) the following: * Processor architectures * Memory hierarchy subsystems * Multiprocessors and multicomputers * Storage and interconnect subsystems * Application-specific, reconfigurable, and embedded architectures * Power-efficient architecture * Dependable architectures * Impact of technology on architecture * Impact of application characteristics on architecture * Architectures for emerging technologies and applications * Performance/power evaluation and measurement of real systems The DEADLINE for abstract submissions (300 - 600 words) is OCTOBER 31, 2003 at 11.59PM PST (US). FULL PAPERS are due on November 7, 2003 at 11.59PM PST (US). NO EXTENSION WILL BE GRANTED!!! NOTIFICATION of acceptance/rejection will be given on FEBRUARY 17, 2004. FINAL VERSIONS of the accepted papers are due on MARCH 24, 2004. As in previous years, a series of tutorials and workshops will be held immediately preceding the symposium. Tutorial and workshop proposals will be accepted until November 14, 2003. If you wish to organize a tutorial (1/2 or 1 day), e-mail a proposal to the Tutorials Chair (Timothy Pinkston, tpink@charity.usc.edu), including title, brief description of topics to be covered, and bio of the speakers. If you wish to organize a workshop (1 or 2 days), e-mail a proposal to the Workshops Chair (Sally A. McKee, sam@csl.cornell.edu), including title, brief description of topics to be covered, and bio of the organizers. Notification of tutorial and workshop decisions will be emailed back to authors on December 15, 2003. Summary of important dates: Abstract submission deadline: Oct 31, 2003 Paper submission deadline: Nov 7, 2003 Workshop/tutorial proposal deadline: Nov 14, 2003 Workshop/tutorial proposal notification: Dec 15, 2003 Paper acceptance notification: Feb 17, 2004 Final paper due: Mar 24, 2004 Please refer to http://isca.in.tum.de for the complete call for papers and other details about the symposium. -- -------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe